Abstract
Abstract A systematic procedure for fault modelling of CMOS circuits is described. It starts with the physical fault and produces a set of tables describing the logic behaviour of the gate. This set of tables is referred to as the fault model and includes truth tables, fault equivalence tables, fault coverage tables, and fault propagation tables. Starting with the procedure of fault modelling of simple combinational circuits, a method is advised for model generation of complex sequential structures. Application of fault modelling for yield evaluation and test pattern generation is considered, too.
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