Physical failures and fault models of CMOS circuits

Abstract

As CMOS has emerged as an important technology for VLSI, testing of large CMOS networks has become a crucial issue. This paper considers single physical failures in a CMOS gate and shows their effect in terms of logic faults. The existence of such a correspondence is verified by simulation results, and a transistor-level fault model is given. To make the test process simpler, a comprehensive fault model of CMOS circuits wherein CMOS stuck-open (s-op) faults are transformed into the classical gate-level TTL stuck-at (s-a) faults has been obtained. This transformation makes the testing of CMOS combinational circuits equivalent to the testing of transformed TTL sequential circuits and eliminates any need for special consideration of s-op faults. The superiority of this gate-level model over other models is its ability to be integrated into the cell libraries of existing automatic test pattern generation (ATPG) packages. This model is also useful for multiple faults when either s-a or s-op faults, or both, are present. Several examples are included to illustrate the versatility and usefulness of this gate-level fault model.