Fan-out WLP — The enabler for system-in-package on Wafer Level (WLSIP)

Abstract

With increasing focus on system approaches, also advanced semiconductor packaging becomes more diversified and fairly more complex. Development of the so called "More-than-Moore" (MtM) solutions, the heterogeneous integration of more functionality, distributed on a number of single elements inside the package, on less footprint and height, is resulting in System-in-Package (SiP) solutions. Chip-Package-Board Co-Design and Co-Development are becoming essential keys for the success. While today the majority of SiP is realized using laminated organic substrate based packages, like BGA and LGA, the need to close the gap to System-on-Chip (SoC) performance, where short connections between the functional areas are inherent, is already visible. Closer distance of the single functional elements to each other is gaining importance for high performance applications. The application of Wafer Level Packaging (WLP) technology is the consequent next step to address this issue. Reduced form factor and package height can be realized. On top, WLP allows efficient large scale batch processing, resulting in lower cost and higher yield in the long run. The limits of Fan-In Wafer Level Packaging (FI-WLP) are addressed by Fan-Out Wafer Level Packaging (FO-WLP), which is the enabler for System-in-Package on Wafer Level (WLSiP). The paper presents an up-to-date overview about the status of the work done at NANIUM related to FO-WLP as enabler for WLSiP. In this stage of the work, it will focus on the "Enabler of the Enabler", means technology and design features needed as building blocks inside the FO-WLP based WLSiP, to go the next step from Single Die FO-WLP to Multi Die FO-WLP and WLSiP.