Abstract
The proliferation of advanced IC package configurations is driving the need for new tool failure analysis (FA) tool development. Although scientists and engineers in the semiconductor industry developed new tools and techniques based on Moore’s Law, with its need to analyze ever-smaller devices, the advent of three-dimensional packaging schemes requires new tools. In this paper we quickly review the existing tools used for package-level FA and introduce several new techniques that aid with this type of analysis. We also discuss the problems and challenges moving forward for this type of tool development.
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