Failure analysis of lead-free solder joints for flip chip on board

Abstract

With the great environmental concern, lead-free solders gradually replace lead-based solders in electronic packages. However, the relatively short history of lead-free solders makes their reliability database inadequate. In other words, there is an urgent need to establish the reliability information of lead-free solders. In this study, a failure analysis is conducted to investigate the reliability of lead free solders. The test vehicle is the flip chip on board (FCOB) with the size of 8 mm*8 mm*0.29 mm, 0.5 mm pitch and an I/O array of 16times16 balls. The device is chosen for its recent popularity in the semiconductor packaging industry. The device includes the silicon chip, solder balls, polymeric underfill and substrate. The analysis is performed by a 3D finite element model. Both 96.5Sn/3.5Ag and 63Sn/37Pb solders are examined for their reliability by accelerated thermal cycling test (ATC) with temperatures ranging from -40degC to 150degC. This approach is used because solder joints are the weakest interconnection of the FCOB and the thermal stress induced low cycle fatigue due to mismatch in the coefficient of thermal expansion (CTE) is the key failure cause. The steady state forced convection and time- dependent elastic strain conditions are adopted. The reliability prediction is evaluated through the Kanchanomai model for 96.5Sn/3.5Ag solder balls and the Engelmaier model for 63Sn/37Pb solder balls, respectively. The simulation results indicate that the outmost solder joint has the largest Von Mises stress and strain for both lead-free and lead-based solders. The delamination between the chip and substrate is affected by the thermal-stress induced by the mismatched CTE. The reliability for lead-free solder 96.5Sn/3.5Ag can reach to 70% or above of the lead-based 63Sn/37Pb solder.