Factors for negative bias temperature instability improvement in deep sub-micron CMOS technology

Abstract

Negative bias temperature instability (NBTI) in PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. A comprehensive study has performed to improve the device NBTI performance by process optimization. It is found that the most effective ways to reduce the NBTI degradation are to control the nitrogen concentration and profile in the nitrided gate oxide, to implement LDD and source/drain implantation by BF2 instead of by B, and to employ a lower annealing temperature and a more diluted H2/N2 mixture. It is seen that the nitrogen incorporation mainly results in more oxide traps. By optimizing the decoupled plasma nitridation (DPN) process, the nitrogen peak/profile should be controlled away from the oxide/Si interface, thus reducing the oxide trap and improving NBTI performance. Incorporation of fluorine species during source/drain implantation can reduce both interface traps and oxide traps.