NBTI performance enhancement with process integration of High Current Fluorine incorporation and O2 gas asher process in 45nm CMOS technology

Abstract

In common agreement with Negative Bias Temperature instability (NBTI) as a serious Front-end reliability issue, great efforts were made in recent years to investigate NBTI mechanism, characterization techniques and performance improvement. In this work authors focused on device NBTI performance improvement from combined impact of multiple process steps integration relating to SiON/Si interface quality. The effect of process integration of High Current Fluorine incorporation in Source/Drain extension along with O2 gas Asher process for post poly resist strip (PRS) and spacer etch process (SPE) on NBTI performance for thin gate regular Vt transistor and SRAM were investigated. Through our work, we demonstrated that by correctly chosen thermal budget and nitrogen profile, the high current fluorine implantation in S/D extension and O 2 gas asher process decrease interface state component of NBTI to greater extent and thus facilitate to achieve enhanced NBTI performance to meet end-of-lifetime specifications.