Study on NBTI improvement of HfO<inf>2</inf>-based 14 nm P-type FinFET with post high-k deposition thermal treatment

Abstract

Negative Bias Temperature Instability (NBTI) of P-type FinFET device remains a major device reliability concern in sub-16/14 nm nodes. In this paper, the impact of HKMG stack process on the NBTI performance is the focus. Especially, post high-k deposition thermal treatment including PDA and PCA process is utilized to improve the NBTI performance of HfO 2 -based P-type FinFET device. The intrinsic mechanism for the reliability improvement using different annealing temperature is disclosed. The intrinsic correlation between annealing temperature and reliability improvement is also investigated. Results show that both PDA and PCA processes can lead to improved NBTI performance due to the restoration of Si/IL interface trap states, as well as the IL regrowth. As the increasing of annealing temperature, the improvement is enhanced. Furthermore, NBTI performance is more sensible to the variation of PDA temperature than PCA temperature. Finally, by optimizing the joint PDA & PCA thermal treatment processes, the NBTI performance is improved significantly.