Fabrication of ultra-thin-film SOI transistors using the recessed channel concept

Abstract

In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer better scaling properties than bulk transistors due to suppressed short channel effects, reduced parasitic capacitance and easy lateral isolation. The objective of this work was to establish a fabrication scheme for the production of fully depleted (FD) SOI transistors with channel thicknesses of 20 nm and below. An SEM based direct write electron beam lithography was used to pattern structures in the sub 100 nm range. Special emphasis was put on the pattern transfer which is accomplished by high-density plasma etching using hard masks and subsequent resist free silicon patterning with a high density HBr/O 2 plasma. This enabled transistor channels as thin as 1 nm to be produced. Together with standard CMOS production processes NMOS and PMOS transistors with gate lengths down to 48 nm have been fabricated and electrically characterized. In this way recessed channel SOI transistors with channel thicknesses below 10 nm and gate lengths smaller than 50 nm have been achieved for the first time.