Self-cascode SOI versus graded-channel SOI MOS transistors

Abstract

Two strategies to enhance transistor performance in SOI technology without increasing the operating voltage are compared. The first option is the use of the self-cascode transistor, a series connection of two conventional FD SOI MOSFETs which, with an appropriate choice of sizes, work as a single transistor with reduced output conductance. The second option is the use of the graded-channel (GC) SOI MOSFET, consisting of a modification of the fully-depleted (FD) SOI MOSFET which leads to better performance of the device in saturation. The paper shows the existing analogy between the operation of self-cascode and GC SOI transistors. The comparison between both strategies is carried out on the basis of simulations with the University of Florida SOI (UFSOI) model and experimental measurements. The area consumed by a self-cascode SOI transistor is estimated to be 10 times larger than that of a GC SOI transistor for the same improvement in output conductance. Experimental results validate the model used for the GC SOI device and also provide numerical quantification of output resistance increase in both configurations.