Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs

Abstract

Fully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode — SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors M S and M D , with channel lengths L S and L D , and threshold voltages V T, S and V T, D , respectively (with V T, S = V T, D in the symmetric SC — S-SC). Recent works [5, 6] showed that the use of different threshold voltages (V T ) for M S and M D (so-called asymmetric self-cascode — A-SC) is able to further enhance the analog properties of SC n- and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n- and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7].