Abstract
It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.
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