Abstract
It is experimentally demonstrated that the novel ion-bombardment-retarded etching (IBRE) process can be applied to fabricate p-channel (p-ch) vertical double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) on bulk Si substrates. By utilizing the IBRE process, p-ch vertical DG MOSFETs with 12- to 42-nm-thick Si vertical channels have been successfully fabricated for the first time. The fabricated vertical DG MOSFETs clearly exhibit the unique nature of the DG structure, i.e., the short-channel-effect (SCE) immunity by decreasing the channel thickness. It is shown that a very low S-slope and relatively high current drive are successfully achieved for the p-ch vertical DG MOSFET with the thinnest channel thickness.
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