Fabrication of TSV-based silicon interposers

Abstract

Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed “TSVs last”, following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a “TSVs first” process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cu-filled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.