Fabrication and testing of thin silicon interposers with multilevel frontside and backside metallization and Cu-filled TSVs

Abstract

Thin silicon or glass interposers provide a path to highly integrated microsystems. In this work we present a process for the fabrication and bonding of 100 and 200 μm thick silicon interposers with frontside and backside multilevel metal (MLM) routing layers and copper filled through-silicon vias (TSVs) with the aspect ratio of 4:1. First, we show the results of a study done to evaluate the compatibility of two types of temporary wafer bonding systems with the deposition, patterning, and cure of three different spin-on dielectric polymers used in the MLM structures. This study also examines bonding of the interposer die to a substrate and the removal of the supporting carrier. Secondly, we describe the process for the fabrication of the Si interposers and present results of electrical testing. Electrical testing before and after thermal cycling revealed a greater than 99% yield of TSVs and a high level of electrical isolation between TSVs. In this paper we demonstrate that a silicon interposer fabrication process using the combination of polymer dielectrics, plated copper routing lines, copper TSVs, and temporary wafer bonding can produce high yielding and robust structures.