Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications

Abstract

In this paper, we explore an approximate logic synthesis approach to re-design adders for error-resilient applications. The objective is that the re-designed approximate adder reduces delay, power and area metrics, and thus, improves both functional and parametric yields due to decrease in the silicon area and delay, respectively. To ameliorate the Error Distance (ED) and Error Rate (ER) of the proposed approximate adder, we avail of the probability of carry-lifetimes and Error Detection and Correction (EDC) logic, respectively. We design the successive versions of the proposed approximate adder using PTM 32nm CMOS technology and simulate the net-lists in HSPICE environment. Simulation results show that for a 16-bit Ripple Carry Adder (RCA) with k = 6, 8 and 10 (k is the number of MSBs that are performed accurately), the proposed approach improves chip yield by 79.08%, 65.81% and 43.72%, and 89.63%, 74.44% and 52.63% with and without EDC logic, respectively.