Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs

Abstract

In chip-multiprocessors with increasing the number of cores, power consumption becomes the main concern in Last Level Cache (LLC). Emerging technologies, such as three-dimensional integrated circuits (3D ICs) and non-volatile memories (NVMs) are among the newest solutions to the design of dark-silicon-aware multi/many-core systems. Although NVMs have many advantages like low leakage and high density, they suffer from shortcomings such as the limited number of write operations and long write operation latency and high energy. In this paper, we use the non-uniform distribution of the accesses and the writes in banks of LLC to improve the lifetime of NVM in LLC and decrease energy consumption. We propose a new hybrid cache design that consists of SRAM banks and STT-RAM banks. Experimental results show that the proposed method improves the energy-delay product by about 43% on average under PARSEC workloads execution. Moreover, this technique improves performance by about 7% on average compared to the conventional methods with STT-RAM cache technology under PARSEC workloads execution.