TAPAS

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3D integration enables large last level caches (LLCs) to be stacked onto a die. In addition, emerging Non Volatile Memories (NVMs) such as Spin-Torque Transfer RAM (STT-RAM) have been explored as a replacement for traditional SRAM-based LLCs due to their higher density and lower leakage power. In this paper, we aim to use the benefits of the integration of STT-RAM in a 3D multi-core environment. The main challenge we try to address is the high operating temperatures. The higher power density of 3D ICs might incur temperature-related problems in reliability, power consumption, and performance. Specifically, recent works have shown that elevated operating temperatures can adversely impact STT-RAM performance. To alleviate the temperature-induced problems, we propose TAPAS, a low-cost temperature-aware adaptive block placement and migration policy, for a hybrid LLC that includes STT-RAM and SRAM structures. This technique places cache blocks according to their temperature characteristics. Specifically, the cache blocks that heat up a hot bank are recognized and migrated to a cooler bank to 1) enable those blocks to get accessed in a cooler bank with lower read/write latency and 2) reduce the number of accesses to the hotter bank. We design and evaluate a novel flow control mechanism to assign priorities to those cache blocks to reach their destination. Evaluation results reveal that TAPAS achieves, on average, 11.6% performance improvement, 6.5% power, and 5.6°C peak temperature reduction compared to a state-of-the art hybrid cache design.