Exploiting and evaluating the potentials of the link addition method for NoC transient error mitigation

Abstract

Transient errors in a Network on Chip (NoC) result in some problems such as network blockage, packets loss or incorrect delivery, which would decrease the network throughput and degrade the successful delivery rate. Many fault tolerant mechanisms, such as error correcting code, retransmission and redundancy for the NoC, have been proposed to mitigate transient errors and guarantee the communication quality. Different from these existing methods, the paper aims at exploiting the potentials of the link addition strategy for transient error alleviation. The regular link addition as well as the customized link addition based on Mesh is designed for alleviating NoC transient errors. The regular design is suitable for the general purpose case while the partially customized design exploits the inherent communication characteristics and the reliability requirement of applications for some specified cases. The experimental results for typical network benchmarks confirm that the proposed link addition methods are effective to improve NoC performance and reliability. (1) In the case of the regular link addition, 4×4 Torus brings the throughput to increase by 45.76% and 87.34% over Mesh for the transpose traffic and the uniform traffic respectively. The reliability metrics of Torus over Mesh are up to 56.65% and 12.71% for the transpose traffic and the uniform traffic respectively. (2) The novel customized reliability-aware link addition mechanism makes the throughput improvement up to 17.4%, 53.5% and the reliability metric up to 16.34%, 57.76% over standard Mesh for the transpose traffic and the hotspot traffic respectively. In addition, the area overhead and power consumption of NoCs are also evaluated by the tool—Orion in the paper.