Asynchronous NoC with Fault tolerant mechanism: A Comprehensive Review

Abstract

The Network on Chip (NoC) is a cost-effective alternative to bus-based connectivity in most multi-core networks. The NoC system solves the drawbacks of bus-based networks by providing higher scalability and dependability. The NoCs are modeled synchronously with the help of global clocks in general. These global clocks are disseminated over vast distances in synchronous NoCs with a modest degree of skew. For high-performance NoC designs that need an expensive customized calibration procedure, a significant global tree is required. As a result, asynchronous NoCs provide an alternate solution to the global clock distribution difficulties. NoC is represented using asynchronous circuits and managed through handshake protocols to tackle global clock difficulties. The Quasi-Delay Insensitive (QDI) circuits are different from DI circuits with time relaxation. The wire delays in QDI circuits are rapidly regulated and incorporated in most practical asynchronous systems, unlike DI-based designs. This manuscript discusses existing ANoC based architecture with fault tolerant mechanisms in detail. The Summary of the current approach, and its performance metrics realization, is highlighted. The challenges and possible solutions for ANoC and its fault-tolerant mechanism are discussed.