Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases

Abstract

The authors have implemented three concurrent fault simulation algorithms and applied them to several circuit families. The algorithms are concurrent fault simulation (CFS), hierarchical concurrent fault simulation (HCFS), and a modification of HCFS called bundled hierarchical fault simulation (BHCFS). In BHCFS, a structure is imposed upon the simulation error lists, which can produce a significant reduction in simulation run time. A prototype of each algorithm has been applied to circuit families of varying size to generate actual run-time data. The circuits are scalable (to some granularity) in gate count. This property allows the simulator run-time data to be presented as a function of circuit size without the effects of varying circuit topology. It is shown experimentally that the run time for BHCFS grows nearly linearly with acyclic circuit gate count but approaches a higher order in tightly connected sequential circuits. It is also confirmed that HCFS exhibits near N log N behaviour in circuits which have reasonably well-balanced design hierarchy. In absolute run time, both hierarchical algorithms outperformed flat CFS at the gate level in all examples except one, which had an extremely unbalanced hierarchy. Overall, BHCFS shows the best performance in acyclic circuits and good performance in loosely coupled sequential circuits. >