Hierarchical fault simulation using behavioral and gate level hardware models

Abstract

This paper presents a fault simulation environment that takes advantage of available models at the behavioral and gate levels of abstraction. The simulation takes place in VHDL and for fault simulation, special VHDL models are written that are capable of propagating circuit faults. Behavioral VHDL models propagate fault effects that appear on their input ports; in addition to this, gate level VHDL models are capable of injecting faults on their output lines. The fault simulation environment assumes the existence of the gate level and behavioral models for every component, and uses the appropriate model depending on whether a fault belongs to it or another component. A wrapper simulation model that encloses both models of a component switches automatically between the models. The wrapper takes care of feedback in the sequential circuits by always selecting the gate level of a component for propagating its own faults. This environment fits well with the hardware description language settings in which pre-synthesis behavioral models, post-synthesis gate-level models and a mixed simulation environment are available. The paper shows a mathematical analysis illustrating the performance improvement of this method over the traditional gate-level fault simulation.