Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms

Peter J Ashenden,Henry Detmold,Wayne S Mckeen

doi:10.1155/1994/86178

Peter J Ashenden, Henry Detmold + Show 1 more

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https://doi.org/10.1155/1994/86178

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Journal: VLSI Design	Publication Date: Jan 1, 1994
Citations: 2	License type: CC BY 3.0

Affiliation: University of Adelaide

Abstract

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.

Highlights

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL
This framework is appropriate for simulating Correct execution of a simulation model can be VHDL models, since such models consist of pro- guaranteed if the following causality constraint is satcesses that represent the behavior of circuit com- isfied: that a process receives and acts upon events ponents, and that schedule and react to changes of in non-decreasing time-stamp order
If two transactions with the same timestamp are sent to a logical process, one of which causes a VHDL event resulting in resumption of the VHDL process, both transactions must be received and the signal value updated before the VHDL process is resumed

Summary

INTRODUCTION

Ver the course of the last decade, VLSI circuits being manufactured have escalated in complexity. Cess by modifying its internal state using the infor- These techniques model a system as a collection of mation in the message, and by sending further logical processes, which interact by scheduling and messages with later time-stamps to other logical proreacting to events that occur at instants in simulation cesses. This framework is appropriate for simulating Correct execution of a simulation model can be VHDL models, since such models consist of pro- guaranteed if the following causality constraint is satcesses that represent the behavior of circuit com- isfied: that a process receives and acts upon events ponents, and that schedule and react to changes of in non-decreasing time-stamp order. This search involves some model specific knowledge about the behavior of processes

Centralized Queue PDES

Conservative Distributed Algorithms

Transport and Inertial Delay Semantics

Initial Implementation

Results

CONCLUSIONS