Examination of novel high-voltage double-emitter horizontal current bipolar transistor (HCBT)

Abstract

Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and to limit the electric field across the intrinsic base-collector junction. This is accomplished by the transistor layout i.e. the mask design. Transistors with BV CEO =12.6 V, V A =301 V and f T =12.7 GHz are fabricated in a standard HCBT BiCMOS process flow without the use of the additional lithography masks. Physical behavior of the transistor is thoroughly examined by 3D device simulations.