Abstract
Rapid growth in size and complexity of modern SoCs results in numerous architectural changes in design for test (DFT) and design for debug (DFD). Understanding the challenges and tracking the advances in DFT and DFD (DFx) design and architecture are essential for correct architecture planning of the next generation of SoCs. This paper provides an insight into the evolution of Graphics Northbridge (GNB) DFx architectures across four generations of AMD Application Specific Integrated Circuit (ASIC), including the first AMD fusion accelerated processor unit (APU).
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