Abstract
In this paper, an ideal lateral insulated gate bipolar transistor (LIGBT) using 0.25μm Silicon-on-insulator (SOI) BiC-DMOS process has been presented. We achieved the significant improvement of the 200V n-type LIGBT (n-LIGBT) current capability by applying hole and electron injection control, optimizing the N+/P+ widths in emitter region, shrinking the emitter-collector pitch, thinning the thickness of the gate insulator, reducing parasitic resistance and optimizing the profile of P-base impurity. The proposed device achieved the current increase by more than double compared with the previous technology. In addition, we improved short circuit capability of n-LIGBT by optimizing the structure and impurity profile. With the proposed n-LIGBT and other optimized devices, we have been able to realize 57% shrinkage in the PDP scan driver IC size compared with the previous one.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
