Abstract

The development of devices that can modulate their conductance under the application of electrical stimuli constitutes a fundamental step towards the realization of synaptic connectivity in neural networks. Optimization of synaptic functionality requires the understanding of the analogue conductance update under different programming conditions. Moreover, properties of physical devices such as bounded conductance values and state-dependent modulation should be considered as they affect storage capacity and performance of the network. This work provides a study of the conductance dynamics produced by identical pulses as a function of the programming parameters in an HfO2 memristive device. The application of a phenomenological model that considers a soft approach to the conductance boundaries allows the identification of different operation regimes and to quantify conductance modulation in the analogue region. Device non-linear switching kinetics is recognized as the physical origin of the transition between different dynamics and motivates the crucial trade-off between degree of analog modulation and memory window. Different kinetics for the processes of conductance increase and decrease account for device programming asymmetry. The identification of programming trade-off together with an evaluation of device variations provide a guideline for the optimization of the analogue programming in view of hardware implementation of neural networks.

Highlights

  • Common hardware logic based on von Neumann paradigm is increasingly facing a bottleneck due to data transfer between separated processing and memory units

  • Conductance increase and decrease dynamics is characterized by pulsed measurements in a wide space of the programming parameters varying the time width and voltage amplitude (Δt and ΔV) of the applied pulses while keeping constant the initial state of the memory cell

  • For low enough ΔV, i.e. in the first few sequences up to the dashed line, no switching occurs and the conductance value does not change during the pulse sequence since the effect of each pulse is so low to result in no visible change of the cumulative conductance

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Summary

Introduction

Common hardware logic based on von Neumann paradigm is increasingly facing a bottleneck due to data transfer between separated processing and memory units. Because of the large number of synapses compared to neurons[7,8], the full potential in terms of scalability, low power and high density can be unlocked only by developing a dedicated device with the ability to dynamically change the synaptic efficacy in response to variable input conditions[9] In this respect, memristive devices and especially resistance random access memories (RRAM)[10,11] have been recently identified as ideal candidates[8,12,13] because of their simple two terminal structure and promising scalability potential[14], non volatile memory[15,16] and low power consumption[17]. The linear behaviour is usually displayed only up to a certain number of pulses and in a restricted memory window Another class of researches analyzes the impact of device dynamics and number of conductance levels on the performance of simulated neuromorphic networks[34,37,38]. In the most general case of unbalanced probabilities of synaptic potentiation and depression, Fusi and Abbott[42] noticed the advantage in terms of memory capacity of softly bounded synaptic weights, in which the weight boundaries are approached asymptotically as the weight update tends to zero

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