Hardware implementation of neural network with expansible and reconfigurable architecture

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In this paper, we propose a new architecture for hardware implementation of digital neural network, called ERNA (expansible and reconfigurable neural network architecture). By adopting flexible ladder-style bus and internal connection network into the digital neural network based on traditional SIMD architecture, the proposed architecture enables fast processing that is based on parallelism and pipelining, while does not abandon the flexibility and expandability of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation learning for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspects of performance and flexibility.