Evaluation technique for plasma-induced SiOC dielectric damage by capacitance–voltage hysteresis monitoring

Abstract

We propose an electrical method, named capacitance–voltage (C–V) monitoring, for quantifying plasma-induced damage (PID) to interlayer dielectrics. By this method, we measure the C–V hysteresis loops to assign carrier trap sites created by PID, and simultaneously obtain the change in the dielectric constant and thickness. We optimized the bias-sweep configuration for measuring the hysteresis curves. It is found that the C–V curve shifted in the negative direction during the optimized voltage sweep from accumulation to inversion in a pseudo-metal–oxide–semiconductor (MOS) structure. This implies the appearance of net positively charged sites owing to PID, presumably near the surface of the SiOC film. We estimate the density of defects created near the surface by monitoring the obtained C–V hysteresis curve shift. Since the degradation of interlayer dielectrics affects the circuit performance, the proposed quantitative method should be used for plasma process designs.