Abstract
For a better comprehension of Plasma Induced Damage (PID) a Short Loop (SL) wafer concept was developed. These wafers can be used for the purpose of monitoring, process development, and tool characterization in different processes. The process of High Density Plasma (HDP) deposition for Inter Layer Dielectrics (ILD) has been investigated using the SL wafer concept. Monitoring data will be presented and it will be shown how irregularities in the process can generate PID. The process sequence can lead to a deposition at the edge of the chuck which is clearly identified as the reason for charging damage. It is shown that the damage risk can be minimized by PID monitoring using the SL wafer concept and by an extended process control.
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