Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

Mahroo Zandrahimi,Zaid Al-Ars,Philippe Debaud,Armand Castillejo

doi:10.1007/s10836-019-05797-w

Mahroo Zandrahimi, Zaid Al-Ars + Show 2 more

Open Access

https://doi.org/10.1007/s10836-019-05797-w

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Abstract

With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.

Highlights

Power is one of the primary design constraints and performance limiters in the semiconductor industry
The number of chip samples should be representative of the process window to make sure that all kind of process variations are taken into account for the correlation process. – Characterization: To be able to use Process Monitoring Boxes (PMBs) for adaptive voltage scaling (AVS) during production, the correlation between PMBs frequency and the actual application behavior is measured during characterization stage
To understand if delay testing is a reasonable performance indicator that can be used for AVS during production, we compared the maximum frequency at which each delay pattern set can be performed for each benchmark versus static timing analysis (STA) results

Summary

Introduction

Power is one of the primary design constraints and performance limiters in the semiconductor industry. AVS approaches embed several PMBs in the chip architecture so that based on the frequency responses of these monitors during production, the chip performance is estimated and the optimal voltage is adapted exclusively to each operating point of each manufactured chip. Offline AVS approaches estimate optimal voltages for each target frequency during production, while online AVS approaches measure optimal voltages during run-time by monitoring the actual circuit performance. For offline AVS approaches, since there is no interaction between PMBs and the circuit, the correlation between PMB responses and the actual performance of the circuit is estimated during the characterization phase using the amount of test chips representative of the process window. Since there are discrepancies in the responses of same PMBs from different test chips, the estimated correlation between the frequency of PMBs and the actual performance of the circuit could be very pessimistic, which results in wasting power and performance. In terms of accuracy and tuning effort, online approaches always win [20]

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