Abstract
SiC MOSFETs are promising devices for many power applications. They are replacing Si devices due to the higher performance of SiC material. However, there are some technological issues still unsolved. One of the main problems is the high density of traps at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage and capacitance-voltage characteristics of a SiC MOSFET. The aim of this work is the study of interface traps effects on C-V and I-V curves for a 1200 V SiC MOSFET. The numerical study is adopted to explain the shape of experimental C-V curves of commercial devices.
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