Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA Designs

Abstract

Radiation Hardening By Design is traditionally performed using Triple Modular Redundancy, a very effective technique that introduces high overheads in terms of resources and power. The Reduced Resolution Redundancy technique presented in this work is a new approximate error mitigation technique that uses redundant circuits with lower resolution to perform computations. In this work we evaluate this technique under radiation using two different benchmarks implemented in FPGA, namely a Fast Fourier Transform and an image processing algorithm for a near infrared detector. Experimental results from proton and neutron irradiation, and fault injection campaigns, show that the Reduced Resolution Redundancy hardening technique can effectively mitigate errors with reduced overheads.