Abstract
The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Fault-tolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.
Highlights
As modern digital systems have become increasingly large and complicated, their dependability parameters are of great concern in playing a critical role in supporting next-generation science, engineering and commercial applications [1]
The scrubbing technique can be used with hardware redundant techniques such as Error Correction Code (ECC) or Triple Modular Redundancy (TMR) techniques in order to improve the reliability of FPGA designs [24]
If we look into the structure of configuration frame in Xilinx FPGAs, it contains an ECC word (a.k.a. checksum) to serve necessary single bit upset correction
Summary
As modern digital systems have become increasingly large and complicated, their dependability parameters are of great concern in playing a critical role in supporting next-generation science, engineering and commercial applications [1]. The FPGA has been involved in various applications in the last couple of decades, such as communication, medical imaging, safety-critical applications [4], [5], [6], [7] These applications are implemented on Static Random Access Memory (SRAM)-based FPGA. Fault-tolerant circuits on SRAM-based FPGA can be implemented by two methods. The first method comprises developing a new FPGA matrix for fault-tolerant components. Another method is based on redundancy applying to the FPGA architecture [2].
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