Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology

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SUMMARYIn the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage Vdd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10−14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd.