Enhanced Ground Bounce Noise Reduction in a Low Leakage 90nm 1-Volt CMOS Full Adder Cell

Abstract

In nanometer regime, ground bounce noise and noise immunity are becoming important metric of comparable importance to the leakage current and active power for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell is proposed for mobile applications with low ground bounce noise. A novel approach has been introduced with stacking power gating technique for further reduction in the peak of ground bounce noise during the sleep to active mode transition. The simulation results depicts that the proposed design leads to efficient 1bit full adder cell in terms of standby leakage power, active power, ground bounce noise and propagation delay. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.