Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications

Abstract

For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. Since, Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher’s attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. Therefore a new transistor resizing approach for 1-bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power has been proposed. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).