Abstract
In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.
Highlights
Advanced clock networks are required in space application for implementation of data handling, communications and attitude orbit control subsystems
When there is a upset in the V_DL output, the missing pulse error is detected by the OSD and instead of propagating the V_DL signal the REF_CLK is propagated if the loop is locked, which is detected by the Lock Detector (LD)
This radiation strike is characterized by two collection phases: a first phase of E-field accelerated free carrier motion followed by a second phase of charge collection which produces a slow current diffusion due to the free carrier density gradients .Since the E-field is present in the space charge region for an off transistor the most sensitive region to an ion strike is the drain terminal [7]
Summary
Advanced clock networks are required in space application for implementation of data handling, communications and attitude orbit control subsystems. With the limited availability of space-qualified clock networking and frequency control, a fully integrated radiation-hardened clock generator solution is needed. (2016) Error Correction Circuit for Single-Event Hardening of Delay Locked Loops. In the literature, hardening of VCDLs has been explored to mitigate the missing pulse errors. The VCDL utilizing complementary differential pair delay cells was proposed in [1] was observed to have missing pulses at frequencies above 1 GHz, due to lower critical charge as a result of technology scaling. The method proposed in this paper simplifies the Single Event Hardened (SEH)technique from [3] while maintaining performance, and generalises the technique from [3] to be able to applied DLL with both single and differential ended VCDL
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