A 70-ns word-wide 1-Mbit ROM with on-chip error-correction circuits

Abstract

A 1-Mb ROM has been developed, organized as either 64K/spl times/16 or 128K/spl times/8 in a pin-selectable option. Multiplexing the address inputs and the data outputs onto the same pins makes it possible to fit into a 28-pin package and to perform straightforward interfacing with some popular 16-bit microprocessors. The process technology is a 1.5-/spl mu/m twin-well double-level-metal CMOS on a grounded p-type substrate. The device uses some dynamic circuitry during the start of the active cycle, but automatically takes itself back into the static precharge state-except for the latched outputs. Typical access time is 70 ns. New high-speed error detection and correction circuits were developed which work in about 10 ns. Because all 16 outputs are not driven at once, but half are delayed by about 15 ns through a process-tracking delay circuit, the on-chip error correction is finished before the process-tracking delay circuit is through, and error correction costs no further access penalty. These error correction circuits enhance both yield and reliability.