Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Abstract

Journal of Circuits, Systems and ComputersVol. 31, No. 18, 2292001 (2022) ErratumFree AccessErratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logicis erratum ofHigh-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS LogicAvadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, and Amit M. JoshiAvadhoot KhairnarDepartment of Electrical Engineering, Indian Institute of Technology, Bombay, India, Bhavuk ChauhanDepartment of Electronics and Communication Engineering, National Institute of Technology, Warangal, India, Geetanjali SharmaDepartment of Electronics and Communication Engineering, Malviya National Institute of Technology, Jaipur, IndiaMaharaja Surajmal Institute of Technology, New Delhi, IndiaCorresponding author., and Amit M. JoshiDepartment of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur, Indiahttps://doi.org/10.1142/S0218126622920013Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail [Journal of Circuits, Systems and Computers, Vol. 31, No. 11 (2022) 2250200 (16 pages)] FiguresReferencesRelatedDetailsRelated articlesHigh-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic8 Apr 2022Journal of Circuits, Systems and Computers Recommended Vol. 31, No. 18 Metrics History Published: 29 October 2022 PDF download