Abstract
A matrix method for the detection of static hazards in combinational logic circuits has been reported (Heal and Page 1993). The method generates 0 and 1-sets of all nodes in each gate level of a circuit progressively until it reaches the output of the circuit. The sets generated are subsequently used to determine the existence of static hazards. This paper introduces enhancements to improve the capabilities and performances of the method, which is applicable to the detection of logic hazards in synchronous combinational logic circuits only. It is shown how certain matrix operations can be simplified to save storage and computation time. A simpler way of determining static hazards is proposed. Required modifications of the method to incorporate the detection of dynamic hazards are presented. It is further shown that the algorithm can also be applied to the transient analysis of digital circuits with exclusive-OR (EX-OR) gates. Examples are given for illustration.
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