Abstract
An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinational logic circuits. The software developed for fault coverage analysis of all single stuck-at faults is simple and fast.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have