Abstract
The effects of diffuse Cu+ in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on the microstructure and performance during a clean etch stopper (CL-ES) process and a back channel etch (BCE) process are investigated and compared. The CL-ES layer formed with a clean component, as verified by TOF-SIMS, can protect the a-IGZO layer from the S/D etchant and prevent Cu+ diffusion, which helps reduce the number of accepter-like defects and improve the reliability of the TFTs. The fabricated CL-ES-structured TFTs have a superior output stability (final Ids/initial Ids = 82.2 %) compared to that of the BCE-structured TFTs (53.5%) because they have a better initial SS value (0.09 V/dec vs 0.46 V/dec), and a better final SS value (0.16 V/dec vs 0.24 V/dec) after the high current stress (HCS) evaluation. In particular, the variation in the threshold voltages has a large difference (3.5 V for the CL-ES TFTs and 7.2 V for the BCE TFTs), which means that the CL-ES-structured TFTs have a higher reliability than the BCE-structured TFTs. Therefore, the CL-ES process is expected to promote the widespread application of a-IGZO technology in the semiconductor industry.
Highlights
Display products have emphasized large areas and high resolutions, and aesthetically pleasing exterior designs [1–3]
Some key Thin-film transistor (TFT) characteristics, the output current stability, cannot satisfy the high current stress (HCS) environment required for Gate drive IC on array (GOA) TFTs [11–13], mainly due to two features of the back channel etch (BCE) process [14]
A-IGZO GOA TFTs with a reduced feature size and clean back channel structure were fabricated via a clean etch stopper (CL-ES) process by batch etching of multilayer amorphous indium-gallium-zinc-oxide (a-IGZO)/ Mo/Cu/Mo
Summary
Display products have emphasized large areas and high resolutions, and aesthetically pleasing exterior designs [1–3]. BCE-structured a-IGZO TFTs have satisfactory characteristics for individual pixel TFTs and the size reduction of GOA TFTs. some key TFT characteristics, the output current stability, cannot satisfy the high current stress (HCS) environment required for GOA TFTs [11–13], mainly due to two features of the BCE process [14]. A clean etch stopper (CL-ES) process, which is less complicated and costly and minimizes contamination, can be used to fabricate a-IGZO-based TFTs with improved uniformity and stability for large-area displays [18]. A-IGZO GOA TFTs with a reduced feature size and clean back channel structure were fabricated via a CL-ES process by batch etching of multilayer a-IGZO/ Mo/Cu/Mo. the influence of the etchant and Cu+ diffusion on the microstructure and performance of CL-ES-structured a-IGZO GOA TFT devices are studied and compared with those of BCE-structured a-IGZO GOA TFT devices. This work provides direct evidence and an insightful demonstration that the improved performance of CL-ES-structured TFTs is highly correlated with its CL-ES structure and its clean components and confirms that the CL-ES process might be an efficient route for the mass production of displays with satisfactory performances
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
