Abstract
Due to the advancement of low power CMOS technology, the fast and low power static random access memory has become an important component of many VLSI chips. This paper is focused on reduction in power consumption during write operation. We have assumed that the proposed SRAM is designed by using Microwind 2 IC design tool with CMOS 0.6μm technology. The proposed SRAM cell is designed with the dual word line approach that is circuit used two separated word line for write (WWL) and read (RWL) operation. In proposed 10 T SRAM with 0.6 μm CMOS technology the average write power consumption is being reduced by using two tail transistor at bottom of pull down network of inverters and the bit line and bit bar line are cross coupled with theses transistor for proper charging and discharging of bit line during write operation. The result is compared with conventional 6T SRAM cell that is also designed with 0.6 μm CMOS technology; there is a decrease in average write power consumption in proposed SRAM by 38.6 %.
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