Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance

Abstract

Achieving sub-60 mV/decade subthreshold swing in short channel Negative Capacitance Field Effect Transistor (NCFET) devices requires the utilization of a thicker Ferroelectric (FE) layer, where due to an interplay between the thickness and polarization gradient of the FE material, undesired effects such as Hysteresis and Negative Differential Resistance (NDR) may be seen in the device characteristics, which limits the expected improvement in the performance. In this work, with a Fully Depleted Silicon-on-insulator (FDSOI) baseline architecture, at a channel length of 14 nm, through utilizing a drain-sided Paraelectric (PE) spacer along with reduced drain doping while laterally splitting the gate stack into two halves such that the nature of the material on the source-sided and drain-sided stack is Ferroelectric and Paraelectric respectively, we show an NDR-free output characteristic. This also enables the incorporation of a thicker FE layer, without observing Hysteresis in the transfer characteristics, while ensuring significantly high Gain (gm/gds) along with sub-60 mV/decade subthreshold swing, at lower supply voltages.