Energy optimization for current-mode signaling in high-speed on-chip interconnects

Abstract

This paper studies the energy-optimization design methodology for current-mode (CM) signaling in high-speed on-chip interconnects, using the modified clamped bit-line sense amplifier circuit (MCBLSA) as a case study. Optimization for the CM circuits for on-chip interconnects requires a completely different treatment than the voltage-mode circuits, due to the problems such as different effective driver resistance and termination resistance modeling. The methodology was validated using SPICE simulations. It is shown that when dealing with receiver termination sizing, the optimal size is determined by the required voltage swing at the receiver end to guarantee valid operation under the effect of crosstalk noise. However, sizing the driver and receiver transistors should be done simultaneously as their resistive values which affect the performance are dependent on each other.