A low power and high performance on-chip interconnect using current mode signalling scheme

Abstract

Current-mode Signalling (CMS) with bias scheme is one of the most promising scheme for high-speed low power communication over long on-chip interconnects. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. When using current mode signalling for on chip interconnects, we obtain a significant improvement in both speed and power consumption. It consumes much less power compared to the current mode signalling feedback scheme. Also current mode signalling derives its advantages over voltage mode due to the reduced swing on the line. By using ring oscillator, buffer, D-latch as a delay element in current mode signalling bias scheme we can reduce the power consumption, delay for on chip interconnect signal transition. Dynamic overdriving method used to improve the performance of current mode signalling bias scheme. That is, current mode transmission can be speeded up by using high drive current. However, this increases static power consumption. One possible solution is to dump high drive current only when the state of the line needs to be changed from 0 to 1 or from 1 to 0. When the line remains at 1 or 0 from one bit to the next, here use a small drive current to maintain the line at the required voltage.