High Speed Current-mode Signaling Circuits for On-Chip Interconnects

Abstract

As the technology scales, the global wire delay becomes a major bottleneck in realizing high performance SOCs. Apart from the technological efforts being made to overcome this problem, it is necessary to develop new circuit design techniques. This paper presents three current-mode circuits for high-speed signal propagation across long on-chip busses. Theoretical analysis has shown that a factor of three can be gained in propagation delay when current-mode (CM) signaling is used in comparison to voltage-mode (VM). In this paper, we show that the delay is reduced by more than a factor of 2 in current mode signaling by using the circuit techniques we propose in comparison to voltage-mode signaling in 0.13 /spl mu/m CMOS technology. This is without any significant power penalty. Further gains in speed are achieved at very high power consumption. The power dissipation on on-chip busses is a strong function of bus layout and data rate. We identified data rates for which the proposed current mode signaling circuits become more power efficient compared to voltage mode signaling circuits.