Abstract
3D Network On Chip(NoC) will provide high multi-core data processing with the minimal amount of energy consumption. It is necessary to consider the architectural limits of three-dimensional NoCs. A deep reinforced framework is proposed that uses router-less NoC for evaluation in the case study. The framework uses prior approaches that may be unreliable because of the difficulties with the design and search process, and the inflexibility that results because of space restrictions. The framework has better loop placements for networking chips with various design constraints. A Monte Carlo search tree is used to develop a Deep Neural Network that searches in parallel for a NoC design.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
