Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

Abstract

In existing CNFET-based design methodologies that are used to implement ternary logic circuits, ternary signals are first converted to binary signals, which are then passed through binary gates and an encoder to get the final ternary output. In a ternary circuit, encoder is used to convert intermediate binary signals to final ternary outputs. This paper presents improved encoder designs that are used in implementation of ternary logic circuits. A detailed analysis is carried out on encoders to understand the effect of using CNFETs with CNTs of different diameter on the overall propagation delay and power consumption of the encoder. Based on this analysis, algorithms, which choose appropriate encoders for different output stages of a ternary circuit while optimizing different design parameters, such as power consumption, propagation delay or power-delay product, are presented. These algorithms are used to map appropriate encoders for different outputs of a ternary adder resulting in adder designs that are optimized for delay, power or power-delay product. Simulation results indicate that the ternary adder designs, which use encoder mapping obtained from proposed algorithms, result in 54%–82% reduction in power consumption, 0%–75% in propagation delay and 54%–94% in power-delay product when compared with different existing ripple carry-based ternary adders.